1. Field of the Invention
The present invention relates to memory cells in semiconductor memory arrays, and in particular, to a memory cell operating within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased when the memory cell is not being accessed.
2. Description of the Related Art
Dynamic random access memories (DRAMs) and static random access memories (SRAMs) typically include a number of storage cells that are organized in arrays having a plurality of rows and columns. In both DRAMs and SRAMs, a word line is associated with each row in the array. In DRAMs, one bit line (BL) is associated with each column in the array. With SRAMs, differential bit lines (BL and BL) are associated with each column in the array. The reading or writing of a particular cell or row of cells in both DRAMs and SRAMs is performed using decoders, sense amplifiers, multiplexer circuits, etc., in a well known manner, and is therefore not explained in greater detail herein.
A DRAM storage cell includes a pass transistor and a storage capacitor having a storage plate and a ground plate. The gate of the pass transistor of the cell is coupled to the word line associated with the row containing the cell. The source of the pass transistor is coupled to the storage plate of the capacitor and the drain is coupled to the bit line associated with the column containing the cell. When the cell is not being accessed (standby mode), the word line associated with the cell is typically held at V.sub.SS (e.g. 0.0 volts). To access the cell, the word line is driven high to VDD (e.g. 3.3 or 5.0 volts), causing the pass transistor to turn on. The pass transistor turns on when the gate potential V.sub.gs (i.e., the word line) exceeds the potential at the source of the transistor by a threshold voltage V.sub.T (e.g., 0.7 volts). During a write operation, the data present on the bit line BL is passed through the pass transistor, and is stored on the charge plate of the capacitor. Alternatively, during a read operation, the charge stored on the charge plate is "dumped" onto the bit line BL, and is then sensed to determine its value.
An SRAM storage cell typically includes two pass transistors and two inverters. The gates of the pass transistors are coupled to the word line associated with the row containing the cell. The source of the first pass transistor is coupled to the output of the first inverter and the input of the second inverter. The source of the second pass transistor is coupled to the output of the second inverter and the input of the first inverter. The drain of the first pass transistor is coupled to bit line BL associated with the column containing the cell. The drain of the second pass transistor is coupled to the differential bit line BL, associated with the column containing the cell. The SRAM stores a charge on the output of one inverter and the complement of that charge on the output of the other inverter. During a read operation, the logic levels stored on the outputs of the inverters are coupled through the pass transistors onto the respective bit lines and sensed. During a write operation, the data placed on the bit line BL is passed through the second pass transistor, is inverted by the second inverter and the inverted signal is stored on the output of the first inverter. The complementary data signal placed on bit line BL is passed through the second pass transistor, is inverted by the first inverter, and is stored on the output of the first inverter.
In prior art DRAM and SRAM storage cells, it is known to apply a negative substrate bias potential V.sub.sb to the pass transistor. The negative substrate bias potential V.sub.sb maintains the pass transistor in a "hard" off state during standby operation of the memory cell, thereby reducing the loss of charge on the storage element due to leakage through the pass transistor. The back bias potential V.sub.sb has the effect of shifting the V.sub.T of the pass transistor, which in turn, reduces the off-leakage current through the device. See for example, Tsukikawa et al., "An Effective Back-Bias Generator with Hybrid Pumping Circuit for 1.5 V DRAMS", IEEE, 1994. The drawback of applying a negative substrate potential V.sub.sb is that it detrimentally affects the switching speed (frequency) of the pass transistor. As a result the average time required to access the cells in the array is increased.
A substantial majority of DRAMs and SRAMs are fabricated using complementary metal oxide field effect transistors (CMOS). As MOSFET technology has evolved, individual MOSFETs have become steadily smaller, e.g. with smaller feature sizes, particularly shorter channel lengths. Smaller transistors has allowed more MOSFETs to be integrated together in one integrated circuit (IC), and has permitted the requisite power supply voltage VDD to become smaller. Benefits of the former include increased operating frequencies, while benefits of the latter include reduced power consumption. However, operating MOSFETs at lower power supply voltages has the undesirable effect of lowering MOSFET current which reduces the maximum operating frequency of the MOSFET. Hence, in order to maintain performance, the MOSFET threshold voltages V.sub.T are reduced so as to minimize a reduction in the MOSFET current. Further discussion of the relationships between power supply voltage, threshold voltage and operating performance for MOSFETs can be found in commonly assigned, copending U.S. patent application Ser. No. 08/292,513, filed Aug. 18, 1994, and entitled "Low Power, High Performance Junction Transistor", the disclosure of which is hereby incorporated by reference. However, lowering the V.sub.T for MOSFETs has the undesired effect of increasing off current, i.e., current leaking through the channel of the MOSFET when the device is turned off.
Accordingly, building DRAM and SRAM devices using low powered and/or threshold MOS devices is problematic because the pass transistors in these devices have a tendency to leak current when the pass transistor are off. Off-leakage current through the pass transistors can cause failure because (1) it may corrupt the data contained in the cell and (2) the charge from a number of cells coupled to a bit line may accumulate on the bit line, which prevents the sense amplifier from sensing the data on the bit line during a read operation.
Yamauchi et al. in the article entitled "A Sub-0.5M A/MB Data-Retention DRAM", IEEE International Solid State Circuits Conference, 1995, and Yamagata et at. in the article entitled "Circuit Design Techniques for Low Voltage Operating and/or Giga-Scale DRAMs", IEEE International Solid State Circuits Conference, 1995 all teach a technique of applying a negative voltage, with respect to Vss, to the gate of a pass transistor of a DRAM memory cell when the memory cell is not being accessed. The negative voltage on the pass transistor biases the transistor off hard, thereby reducing the amount of leakage current through the source and drain of the transistor.